1. Field of the Invention
The present invention relates to a memory configuration comprising a multiplicity of memory cells, which each have at least one ferroelectric storage capacitor and a selection transistor and are addressed via word lines and bit line pairs. It is thereby possible for a reference signal obtained from a reference cell via a bit line pair to be compared with a read signal from a memory cell in a sense amplifier.
It is known in the art that nonvolatile memory configurations can be constructed using ferroelectric dielectrics made, for example, of bismuth barium tantalate (SBT) or lead zirconium titanate (PZT). In the case of such memory configurations, individual memory cells may each comprise a selection transistor and a storage capacitor with a dielectric made of SBT or PZT, resulting in a so-called "1T/1C cell concept". In principle, storage densities similar to those in conventional DRAMs (dynamic random access memories) can be achieved with the 1T/1C cell concept.
In the event of reading a memory cell having a ferroelectric storage capacitor, a so-called FeRAM memory cell, before the actual information is read from the memory cell, it is necessary firstly to generate a reference voltage, which can be done by reading a reference memory cell pair. Only after the reference voltage has been obtained from the reference memory cell pair is the actual memory cell then read, and the read signal obtained from this memory cell is compared with the previously generated reference voltage in the sense amplifier and evaluated.
Such a necessarily "serial" reading cycle requires a relatively long time since the reference voltage and the actual read signal are generated successively with respect to time. To date, there have been no considerations as to how this relatively long period of time might be shortened.
This can probably essentially be attributed to the fact that to date the method employed to read a memory configuration comprising FeRAM memory cells (i.e., a ferroelectric memory configuration) has been a method similar to that employed to read a DRAM: the memory cell to be read, with a storage capacitor having a ferroelectric dielectric made of SBT or PZT for example, is connected to a bit line by means of the selection transistor of the memory cell. A useful signal of the order of magnitude of a few 100 mV is then produced on the bit line on account of the ratios of the capacitances. This relatively small useful signal is amplified to the full logic level in the sense amplifier. For this purpose, however, the sense amplifier requires a reference voltage, which should preferably represent the mean value of the voltages, which is obtained in each case when a logic zero (0) or a logic one (1) is read from a memory cell. The reference voltage can be generated by reading two reference cells on a bit line pair, whereby the reference cells must contain inverse information, that is to say "zero" and "one". The arithmetic mean of the two read signals previously obtained is obtained by subsequent short-circuiting of the bit line pair. The reference signal thus generated with the mean value is left on one of the two bit lines, while the memory cell to be read is then activated on the other bit line. In the sense amplifier, the voltage that has been read out is then compared with the reference voltage and finally amplified to the full logic level.
The sense amplifier concept of the prior art ferroelectric memory configuration with the conventional serial access cycle will be explained below with reference to FIGS. 4 to 6. FIG. 4 shows a memory cell comprising a ferroelectric storage capacitor Cferro and a selection transistor TG. The source or drain of the selection transistor TG is connected to a bit line BL and the gate of the selection transistor TG is connected to a word line WL. The ferroelectric storage capacitor Cferro is connected between the source or drain of the selection transistor TG and a common plate voltage PL.
A memory cell of that type is represented in FIGS. 1, 3 and 5 by the symbol (i.e., bull's eye target) specified in FIG. 4.
FIG. 5 shows the structural circuitry of a conventional memory configuration with the customary sense amplifier concept for a serial access cycle. In this conventional memory configuration, bit line pairs BL &lt;0&gt; and bBL &lt;0&gt; and BL &lt;1&gt; and bBL &lt;1&gt; are connected via selection transistors S in each case to a sense amplifier SA &lt;0&gt; and SA &lt;1&gt;, respectively. What is essential is that, in this existing memory configuration, reference cells R and cells L to be read are in each case electrically connected to the same bit line pair BL &lt;0&gt; and bBL &lt;0&gt;, and BL &lt;1&gt; and bBL &lt;1&gt;, respectively. This means that only sequential generation of the reference voltage by means of the reference cells R and subsequent reading of the memory cells L are possible.
The sequential generation of the reference voltage and subsequent reading of the memory cell will be explained in more detail below with reference to FIG. 6.
A reading cycle begins for example at t=10 ns with a negative edge of a strobe signal. This is then followed by the generation of a reference voltage ref in a time period A. For this purpose, first of all the two bit lines BL &lt;0&gt; and bBL &lt;0&gt;, for example, are discharged to zero volts (operation "pre" in FIG. 6). Two reference cells R at the interfaces between reference word lines REFWL &lt;03&gt; and REFWL &lt;12&gt; with the bit lines BL &lt;0&gt; and bBL &lt;0&gt; with inverse information are subsequently read, which produces a signal "ref". Finally, the arithmetic mean of the reference voltages of the reference cells R is formed by short-circuiting of the two bit lines BL &lt;0&gt; and bBL &lt;0&gt; by means of a short-circuiting transistor SG, which is driven via a short-circuiting line SHT &lt;0&gt; and SHT &lt;1&gt; respectively (cf. time period "short" in FIG. 6).
In a subsequent time period B, the bit line to be read, that is to say the bit line BL &lt;0&gt;, for example, is then discharged to 0 volts (cf. time period "prerd" in FIG. 6), and the memory cell is then read (cf. time period "read" in FIG. 6).
On the bit line BL &lt;0&gt; to be read, a voltage is then present which is less than or greater than the reference voltage, depending on the memory content of the memory cell L to be read. In the subsequent amplification operation during a time period C, this small voltage is amplified to a full logic level (time period "sense").
Approximately at t=70 ns, that is to say approximately 60 ns after the beginning of the read cycle, the information that has been read is thus available for further processing on data lines LDQ &lt;0&gt; and bLDQ &lt;0&gt;. Finally, the information is also written back to the reference cells R (time period "write back") and the assembly is returned to a quiescent state during a time period D.
FIG. 5 additionally shows switching transistors S, which can be driven via control lines MUX &lt;0&gt; and MUX &lt;1&gt; and connect the individual bit lines BL &lt;0&gt;, bBL &lt;0&gt;, BL &lt;1&gt; and bBL &lt;1&gt; to the sense amplifiers SA &lt;0&gt; and SA &lt;1&gt;, respectively. The memory cells L are each located at positions of intersection of the bit lines BL &lt;0&gt;, bBL &lt;0&gt;, BL &lt;1&gt; and bBL &lt;1&gt; with word lines WL &lt;0&gt;, WL &lt;1&gt;, WL &lt;2&gt;, WL &lt;3&gt;, . . . WL &lt;0+n*4&gt;, WL &lt;1+n*4&gt;, WL &lt;2+n*4&gt; and WL &lt;3+n*4&gt;. The memory cells L in this case form a cell array or cell field, as is illustrated diagrammatically in FIG. 5.